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THS4304
www.ti.com
SLOS436A - MARCH 2004 - REVISED JULY 2004
Wideband Operational Amplifier
FEATURES
* * * * * Wide Bandwidth: 3 GHz High Slew Rate: 830 V/s Low Voltage Noise: 2.8 nV/Hz Single Supply: 5 V, 3 V Quiescent Current: 18 mA
APPLICATIONS
* * * * * Active Filter ADC Driver Ultrasound Gamma Camera RF/Telecom
DESCRIPTION
The THS4304 is a wideband, voltage-feedback operational amplifier designed for use in high-speed analog signal-processing chains operating with a single 5-V power supply. Developed in the BiCom3 silicon germanium process technology, the THS4304 offers best-in-class performance using a single 5-V supply as opposed to previous generations of operational amplifiers requiring 5-V supplies. The THS4304 is a traditional voltage-feedback topology that provides the following benefits: balanced inputs, low offset voltage and offset current, low offset drift, high common mode and power supply rejection ratio. The THS4304 is offered in 8-pin MSOP package (DGK), the 8-pin SOIC package (D), and the space-saving 5-pin SOT-23 package (DBV). DIFFERENTIAL ADC DRIVE
+5V 10 k V REF (= 2.5V) RG V REF +5V 85 +3.3 VA +3.3 VD dB RF 10 k 0.1 F Combined THS4304 and ADS5500 SFDR
90
V IN
1: 1 V REF 49 .9
THS 4304 100 +5V THS 4304 100 1nF CM 0.1 F 1nF CM 1k 1k A IN+ ADS 5500 A IN- CM D A
80 G = 10 dB, RF = 249 , RG = 115 , SNR = 69.6, FS = 125 MSPS 10 20 30 40 50
From 50- source
75
V REF RG RF
f - Frequency - MHz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2004, Texas Instruments Incorporated
THS4304
SLOS436A - MARCH 2004 - REVISED JULY 2004
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PINOUT DRAWING
TOP VIEW DBV TOP VIEW D and DGK
VOUT VS- IN+
1 2
5
VS+
NC IN- IN+
1 2 3 4
8 7 6 5
NC VS+ VOUT VOUT
3
4
IN- VS-
NOTE: NC indicates there is no internal connection to these pins.
PACKAGING / ORDERING INFORMATION
PACKAGED DEVICES THS4304DBVT THS4304DBVR THS4304D THS4304DR THS4304DGK THS4304DGKR PACKAGE TYPE SOT-23-5 SOIC-8 MSOP-8 PACKAGE MARKINGS AKW -- AKU TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 3000 Rails, 75 Tape and Reel, 2500 Rails, 100 Tape and Reel, 2500
DISSIPATION RATINGS
PACKAGE DBV (5) D (8) DGK (8) (1) (2) JC (C/W) 55 38.3 71.5 JA (C/W) (1) 255.4 97.5 180.8 POWER RATING (2) TA 25C 391 mW 1.02 W 553 mW TA = 85C 156 mW 410 mW 221 mW
This data was taken using the JEDEC standard High-K test PCB. Power rating determined with a junction temperature of 125C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125C for best performance and long-term reliability.
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT VS VI IO VID Supply voltage Input voltage Output current Differential input voltage Continuous power dissipation TJ Tstg Maximum junction temperature, any condition (2) Operating free-air temperature range, continuous operation, long-term reliability (2) Storage temperature range Lead temperature: 1,6 mm (1/16 inch) from case for 10 seconds HBM ESD Ratings CDM MM (1) (2) +6.0 V VS 150 mA 2 V See Dissipation Rating Table 150C 125C -65C to 150C 300C 1600 V 1000 V 100 V
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN Supply voltage, (VS+ and VS-) Input common-mode voltage range Dual supply Single supply 1.35 2.7 VS-- 0.2 MAX 2.5 5 VS+ + 0.2 UNIT V V
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SLOS436A - MARCH 2004 - REVISED JULY 2004
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ELECTRICAL CHARACTERISTICS
Specifications: VS = 5 V: RF = 249 , RL = 100 , and G = +2 unless otherwise noted
TYP PARAMETER AC PERFORMANCE G = +1, VO = 100 mVpp Small-Signal Bandwidth G = +2, VO = 100 mVpp G = +5, VO = 100 mVpp G = +10, VO = 100 mVpp Gain Bandwidth Product 0.1-dB Flat Bandwidth Large-Signal Bandwidth Slew Rate Settling Time to 0.1% Settling Time to 0.01% Settling Time to 0.001% Rise / Fall Times Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Third-Order Intermodulation Distortion (IMD3) Third-Order Output Intercept (OIP3) Noise Figure Input Voltage Noise Input Current Noise DC PERFORMANCE Open-Loop Voltage Gain (AOL) Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT CHARACTERISTICS Common-Mode Input Range Common-Mode Rejection Ratio Input Resistance Input Capacitance (1) VO = 0.2 V, VCM = 2.5 V Each input, referenced to GND -0.2 to 5.2 95 100 1.5 0.2 to 4.8 80 0.4 to 4.6 73 0.4 to 4.6 73 V dB k pF Min Min Typ Typ A A C C VCM = 2.5 V 7 0.5 12 1 VO = 0.8 V, VCM = 2.5 V 65 0.5 54 4 50 5 5 18 50 1.2 10 50 5 5 18 50 1.2 10 dB mV V/C A nA/C A nA/C Min Max Typ Max Typ Max Typ A A B A B A B RL= 100 G = +2, VO = 2 VPP, f = 10 MHz RL = 1 k RL = 100 RL = 1 k G = +2, VO= 2-VPP envelope, 200-kHz tone spacing, f = 20 MHz G = +2, f = 1 GHz f = 100 kHz f = 100 kHz -84 -95 -100 -100 -84 48 15 2.8 3.8 dBc dBc dBc dBc dBc dBm dB nV/Hz pA/Hz Typ Typ Typ Typ Typ Typ Typ Typ Typ C C C C C C C C C G >+10 G= +2, VO = 100 mVpp, CF = 0.5 pF G = +2, VO = 2 VPP G = +2, VO = 1-V Step G = +2, VO = 2-V Step G = -2, VO = 2-V Step G = -2, VO = 2-V Step G = -2, VO = 2-V Step G = +2, VO = 2-V Step 3 1 187 87 870 300 240 830 790 4.5 7.5 35 2.5 GHz GHz MHz MHz MHz MHz MHz V/s V/s ns ns ns ns Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ C C C C C C C C C C C C C CONDITIONS 25C 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ MAX TEST LEVEL (1)
Test levels: (A) 100% tested at 25C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.
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ELECTRICAL CHARACTERISTICS (continued)
Specifications: VS = 5 V: RF = 249 , RL = 100 , and G = +2 unless otherwise noted
TYP PARAMETER OUTPUT CHARACTERISTICS RL = 100 Output Voltage Swing RL = 1 k Output Current (Sourcing) Output Current (Sinking) Output Impedance POWER SUPPLY Maximum Operating Voltage Minimum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power Supply Rejection (+PSRR) Power Supply Rejection (-PSRR) VS+ = 5.5 V to 4.5 V, VS- = 0 V VS+ = 5 V, VS- = -0.5 V to +0.5 V 5 5 18 18 80 60 5.5 2.7 18.9 17.5 73 57 5.5 2.7 19.4 16.6 66 54 5.5 2.7 19.4 16.6 66 54 V mA mA dB dB Max Min Max Min Min Min A A A A A RL = 10 RL = 10 f = 100 kHz 1.1 to 3.9 1 to 4 140 92 0.016 1.2 to 3.8 1.1 to 3.9 100 65 1.3 to 3.7 1.2 to 3.8 57 40 1.3 to 3.7 1.2 to 3.8 57 40 CONDITIONS 25C 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ MAX TEST LEVEL (1)
V
Min
A
mA mA
Min Min Typ
A A A
5
THS4304
SLOS436A - MARCH 2004 - REVISED JULY 2004
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ELECTRICAL CHARACTERISTICS
Specifications: VS = 3 V: RF = 249 , RL = 499 , and G = +2 unless otherwise noted
TYP PARAMETER CONDITIONS 25C 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ MAX TEST LEVEL (1)
AC PERFORMANCE G = +1, VO = 100 mVpp Small-Signal Bandwidth G = +2, VO = 100 mVpp G = +5, VO = 100 mVpp G = +10, VO = 100 mVpp Gain Bandwidth Product Large-Signal Bandwidth Slew Rate Settling Time to 0.1% Settling Time to 0.01% Rise / Fall Times Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Noise Figure Input Voltage Noise Input Current Noise DC PERFORMANCE Open-Loop Voltage Gain (AOL) Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT CHARACTERISTICS Common-Mode Input Range Common-Mode Rejection Ratio Input Resistance Input Capacitance (1) VO = 0.09 V, VCM = 1.5 V Each input, referenced to GND -0.2 to 3.2 92 100 1.5 0.2 to 2.8 80 0.4 to 2.6 70 0.4 to 2.6 70 V dB k pF Min Min Typ Typ A A C C VCM = 1.5 V 7 0.4 12 1 VO = 0.5 V, VCM = 1.5 V 49 2 44 4 5 5 18 50 1.2 10 5 5 18 50 1.2 10 dB mV V/C A nA/C A nA/C Min Max Typ Max Typ Max Typ A A B A B A B G = +2, VO = 0.5 VPP, f = 10 MHz G = +2, f = 1 GHz f = 100 kHz f = 100 kHz RL = 499 -92 -91 15 2.8 3.8 dBc dBc dB nV/Hz pA/Hz Typ Typ Typ Typ Typ C C C C C G >+10 G = +2, VO = 1 VPP G = +2, VO = 1-V Step G = +2, VO = 1-V Step G = -2, VO = 0.5-V Step G = -2, VO = 0.5-V Step G = +2, VO = 0.5-V Step 3 900 190 83 830 450 750 675 4.5 20 1.5 GHz MHz MHz MHz MHz MHz V/s V/s ns ns ns Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ C C C C C C C C C C C
Test levels: (A) 100% tested at 25C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.
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THS4304
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ELECTRICAL CHARACTERISTICS (continued)
Specifications: VS = 3 V: RF = 249 , RL = 499 , and G = +2 unless otherwise noted
TYP PARAMETER CONDITIONS 25C 25C OVER TEMPERATURE 0C to 70C -40C to 85C 1.3 to 1.7 1.2 to 1.8 40 35 UNITS MIN/ MAX TEST LEVEL (1)
OUTPUT CHARACTERISTIC RL = 100 Output Voltage Swing RL = 1 k Output Current (Sourcing) Output Current (Sinking) Output Impedance POWER SUPPLY Maximum Operating Voltage Minimum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power Supply Rejection (+PSRR) Power Supply Rejection (-PSRR) VS+ = 3.3 V to 2.7 V, VS- = 0 V VS+ = 5 V, VS- = -0.5 V to +0.5 V 3 3 17.2 17.2 80 60 5.5 2.7 17.9 16.5 60 55 5.5 2.7 18.4 15.6 54 52 5.5 2.7 18.4 15.6 54 52 V mA mA dB dB Max Min Max Min Min Min A A A A A RL = 10 RL = 10 f = 100 kHz 1.1 to 1.9 1 to 2 57 57 0.016 1.2 to 1.8 1.1 to 1.9 50 45 1.3 to 1.7 1.2 to 1.8 40 35
V
Min
A
mA mA
Min Min Typ
A A A
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THS4304
SLOS436A - MARCH 2004 - REVISED JULY 2004
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE 5V Frequency response 0.1-dB Flatness Frequency response by package S-Parameters 2nd Harmonic distortion 3rd Harmonic distortion 2nd Harmonic distortion 3rd Harmonic distortion IMD3 OIP3 SR Vn/In Iq VO VOS IIB VOS VO VO VO VO ZO 3V Frequency response 2nd Harmonic distortion 3rd Harmonic distortion Harmonic Distortion SR VO VO IIB VOS VO VO ZO Slew rate Settling time Output voltage Input bias and offset current Input offset voltage Large-signal transient response Overdrive recovery time Output impedance vs Frequency vs Load resistance vs Case temperature vs Case temperature vs Frequency vs Frequency vs Output voltage vs Output voltage 32-35 36 37 38 39 40 41 42 43 44 45 46 3rd Order intermodulation distortion 3rd Order output intercept point Slew rate Noise Noise figure Quiescent current Rejection ratio Output voltage Input offset voltage Input bias and offset current Input offset voltage Open-loop gain Small-signal transient response Large-signal transient response Settling time Overdrive recovery time Output impedance vs Frequency vs Frequency vs Frequency vs Frequency vs Output voltage vs Output voltage vs Frequency vs Frequency vs Output voltage vs Frequency vs Frequency vs Supply voltage vs Frequency vs Load resistance vs Input common-mode voltage vs Case temperature vs Case temperature vs Frequency 1-3, 5, 6 4 7 8 9, 11 10, 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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TYPICAL CHARACTERISTICS (5 V)
FREQUENCY RESPONSE
6 5 4 Signal Gain - dB Signal Gain - dB 3 2 1 0 -1 -2 -3
3 GHz
FREQUENCY RESPONSE
10 9 8 7 6 5 4 3 2 1 CF = 1 pF CF = 0.5 pF Gain = 2, RF = 249 , RL = 100 , VO = 100 mVPP, VS = 5 V 24 22 20 18 Signal Gain - dB 16 14 12 10 8 6 4 2 0 -2 -4 100 k
FREQUENCY RESPONSE
G = 10 RF = 249 , RL = 100 , VO = 100 mVPP VS = 5 V
Gain = 1, RL = 100 , VS = 5 V
VO = 100 mVPP
CF = 0 pF
G=5
VO = 200 mVPP
1 GHz
G=2
VO = 400 mVPP VO = 800 mVPP
G = 1, RF = 0
-4
1M
10 M
100 M
1G
10 G
0
1M
10 M
100 M
1G
10 G
1M
10 M
100 M
1G
10 G
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 1. 0.1-dB FLATNESS
6.4 6.3 6.2 Signal Gain - dB 6.1 6 5.9 5.8 5.7 5.6 1M 10 M 100 M 1G f - Frequency - Hz Gain = 2, RF = 249 , CF = 0.5 pF, RL = 100 , VO = 100 mVPP, VS = 5 V 22 20 18 16 Signal Gain - dB 300 MHz 14 12 10 8 6 4 2 0 -2 -4 1M RF = 0
Figure 2. FREQUENCY RESPONSE
22 90 MHz RF = 249 , RL = 100 , VO = 1 VPP, VS = 5 V Signal Gain - dB 20 18 16 14 12 10 8 6 4 2 0 -2 -4 10 M 100 M 1G 10 G 1M f - Frequency - Hz
Figure 3. FREQUENCY RESPONSE
87 MHz RF = 249 , RL = 100 , VO = 2 VPP, VS = 5 V
200 MHz
175 MHz
240 MHz RF = 0
480 MHz
560 MHz
290 MHz 10 M 100 M 1G 10 G
f - Frequency - Hz
Figure 4.
Figure 5. S-PARAMETERS vs FREQUENCY
-40 SOT-23 0 S21 2nd Harmonic Distortion - dBc -50 -60 -70 -80 -90 -100 Gain = 2 RF = 249 VO = 2 VPP VS = 5 V
Figure 6. 2ND HARMONIC DISTORTION vs FREQUENCY
FREQUENCY RESPONSE BY PACKAGE
10 9 8 Signal Gain - dB 7 6 5 4 3 2 1 0 1M 10 M 100 M 1G 10 G f - Frequency - Hz Gain = 2, RF = 249 , RL = 100 , VO = 100 mVPP, VS = 5 V MSOP SOIC Signal Gain - dB
-20
S22
SOT-23 RL = 100
MSOP RL = 100
-40 S11 -60 Gain = 2, RF = 249 , RL = 100 , VO = 100 mVPP, VS = 5 V 10 M 100 M 1G 10 G S12
-80
MSOP and SOT-23 RL = 499 to 1 k -110 1M 10 M f - Frequency - Hz 100 M
-100 1M
f - Frequency - Hz
Figure 7.
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS (5 V) (continued)
3RD HARMONIC DISTORTION vs FREQUENCY
-30 3rd Harmonic Distortion - dBc
2ND HARMONIC DISTORTION vs FREQUENCY
-40 2nd Harmonic Distortion - dBc
3rd Harmonic Distortion - dBc -40
3RD HARMONIC DISTORTION vs FREQUENCY
Gain = 2, RF = 249 , VO = 1 VPP, VS = 5 V
-40 -50 -60 -70 -80 -90 -100 -110 1M
Gain = 2, RF = 249 , VO = 2 VPP, VS = 5 V
-50 -60 -70
Gain = 2 RF = 249 VO = 1 VPP VS = 5 V SOT-23 RL = 100 MSOP RL = 100
-50 -60 -70 -80 -90 -100 -110
MSOP and SOT-23 RL = 100 to 1 k
-80 -90 -100 MSOP and SOT-23 RL = 499 to 1 k -110 1M 10 M f - Frequency - Hz 100 M
MSOP and SOT-23 RL = 100 to 1 k
10 M f - Frequency - Hz
100 M
1M
10 M f - Frequency - Hz
100 M
Figure 10.
Figure 11.
Figure 12. 3RD ORDER INTERMODULATION DISTORTION vs FREQUENCY
-30 Gain = 2, RF = 249 , RL = 100 , 200 kHz Spacing, VS = 5 V VO = 2 VPP envelope
2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE
-40 3rd Harmonic Distortion - dBc 3rd Harmonic Distortion - dBc -50 -60 -70 -80 -90 -100 SOT-23 RL = 499 to 1 k -110 0 0.5 1 1.5 2 2.5 VO - Output Voltage - VPP 3 SOT-23 RL = 100 Gain = 2, RF = 249 , RL = 100 , f = 10 MHz, VS = 5 V -30 -40 -50 -60 -70 -80 -90 -100 -110 0
3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE
Gain = 2, RF = 249 , RL = 100 , f = 10 MHz, VS = 5 V IMD 3 - dBc
-40 -50 -60 -70 -80 -90 -100
SOT-23 RL = 100 to 1 k
VO = 1 VPP envelope
0.5
1
1.5
2
2.5
3
-110
10 M f - Frequency - Hz
100 M
VO - Output Voltage - VPP
Figure 13. 3RD ORDER OUTPUT INTERCEPT POINT vs FREQUENCY
60
Figure 14.
Figure 15.
SLEW RATE vs OUTPUT VOLTAGE
900 850 Gain = 2, RF = 249 , RL = 100 , VS = 5 V Rise Fall
1000
NOISE vs FREQUENCY
Hz V n - Voltage Noise - nV/
50
800 SR - Slew Rate - V/ s 750 700 650 600 550 500 450
100 M f - Frequency - Hz
I n - Current Noise - pA/
Hz 100 In- In+ 10 Vn 1
OIP 3 - dBm
40
30 Gain = 2, RF = 249 , RL = 100 , VO = 2-VPP envelope, 200-kHz Spacing, VS = 5 V 10 M
20
10
400
0
0.5
1
1.5
2
2.5
3
10
10 k 1k 100 f - Frequency - Hz
100 k
VO - Output Voltage -VPP
Figure 16.
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (5 V) (continued)
NOISE FIGURE vs FREQUENCY
20 18 I q - Quiescent Current - mA 16 Noise Figure - dB 14 12 10 8 6 4 2 0 10 M 500 M f - Frequency - Hz Gain = 2, RF = 249 , RG = 249 , RL = 100 , VS = 5 V 1G 22 20 18 TA = 25C TA = -40C Rejection Ratio - dB 16 14 12 10 8 6 4 2 0 2 2.5 3.5 4.5 3 4 VS - Supply Voltage - V 5 TA = 85C
QUIESCENT CURRENT vs SUPPLY VOLTAGE
110 100 90 80 70 60 50 40 30 20 10 0 10 k CMRR
REJECTION RATIO vs FREQUENCY
VS = 5 V PSRR+
PSRR-
100 k
1M
10 M
100 M
1G
f - Frequency - Hz
Figure 19.
Figure 20.
Figure 21. INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE
9 280 VS = 5 V IIB- 260 240 220 IIB+ 200 180 IOS 2 1 160 140 120 OS - Input Offset Current - nA I VI - Input Voltage - V 8 I IB - Input Bias Current - A 7 6 5 4 3
OUTPUT VOLTAGE vs LOAD RESISTANCE
4 5 4.5 VOS - Input Offset Voltage - mV 3.5 VO - Output Voltage - V 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 10 100 RL - Load Resistance - 1000
INPUT OFFSET VOLTAGE vs INPUT COMMON-MODE VOLTAGE
VS = 5 V
3 VS = 5 V 2.5
2 1.5 1
0
0.5
1
1.5 2
2.5 3
3.5 4
4.5
5
100 0 -40-30 -20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C
VICR - Input Common-Mode Voltage - V
Figure 22. INPUT OFFSET VOLTAGE vs CASE TEMPERATURE
600 VS = 5 V
70 80
Figure 23. OPEN-LOOP GAIN vs FREQUENCY
20 VS = 5 V 0 Gain -20 -40 Phase - -60 Phase -80
VO - Output Voltage - V 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 0
Figure 24.
SMALL-SIGNAL TRANSIENT RESPONSE
2.8 Input 2.7 2.6 2.5 2.4 Output 2.3
VOS - Input Offset Voltage - V
500
Open-Loop Gain - dB
60 50 40 30 20 10 0 -10
400 300 200 100 0 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C
-100 -120 -140 -160 100 k 1 M 10 M 100 M 1 G -180 10 G
Gain = 2 RL = 100 RF = 249 tr/tf = 300 ps VS = 5 V 10 20 30 40 50 60
-20 10 k
f - Frequency - Hz
t - Time - ns
Figure 25.
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (5 V) (continued)
LARGE-SIGNAL TRANSIENT RESPONSE
3.5 VI - Input Voltage - V Input 3 2.5 VO - Output Voltage - V 4 3.5 3 2.5 2 1.5 1 0 10 20 30 40 50 60 Gain = 2 RL = 100 RF = 249 VS = 5 V Output 2 1.5
SETTLING TIME
4
4.5
OVERDRIVE RECOVERY TIME
3.5 Input Gain = 2 RL = 100 RF = 249 VS = 5 V 3.25 VI - Input Voltage - V 3 2.75 2.5 Output 2.25 2 1.75 1.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 t - Time - s
3.5 V O- Output Voltage - V
VO - Output Voltage - V
4 3.5 3 2.5 2 1.5 1 0.5
3 2.5 Gain = 2 RL = 100 RF = 249 VS = 5 V
2 1.5 1
0
1
2
3
4
5
6
7
t - Time - ns
t - Time - ns
Figure 28.
Figure 29. OUTPUT IMPEDANCE vs FREQUENCY
10 k 1k 100 10 Gain = 2, RF = 249 , VS = 5 V
Figure 30.
Z o - Output Impedance -
1 0.1 0.01 100 k 1M 10 M 100 M 1G f - Frequency - Hz
Figure 31.
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TYPICAL CHARACTERISTICS (3 V)
FREQUENCY RESPONSE
10 9 8 Signal Gain - dB 7 6 5
VO = 400 mVPP
FREQUENCY RESPONSE
10 9 8 Signal Gain - dB Gain = 2 RL = 499 RF = 249 , VO = 100 mVPP, VS = 3 V CF = 0 pF CF = 0.5 pF 24 22 20 18 16 14 12 10 8 6 4 2 0 -2 -4 1M
FREQUENCY RESPONSE
G 10 RF = 249 , RL = 499 , VO = 100 mVPP, VS = 3 V
VO = 200 mVPP
6 5 4 3 CF = 1 pF
Signal Gain - dB
Gain = 2 RL = 499 RF = 249 , VS = 3 V
VO = 100 mVPP
7
G5
4
-3dB 900 MHz
G2
3 2 1 0 10 M 100 M 1G 10 G f - Frequency - Hz
VO = 800 mVPP
2 1 0 10 M 100 M 1G 10 G
G 1, RF 0
10 M
100 M
1G
10 G
f - Frequency - Hz
f - Frequency - Hz
Figure 32.
Figure 33. 2ND HARMONIC DISTORTION vs FREQUENCY
-50 2nd Harmonic Distortion - dBc Gain = 2 RL = 499 RF = 249 , VO = 500 mVPP, VS = 3 V -50
Figure 34. 3RD HARMONIC DISTORTION vs FREQUENCY
Gain = 2 RL = 499 RF = 249 , VO = 500 mVPP, VS = 3 V
FREQUENCY RESPONSE
22 20 18 16 Signal Gain - dB 14 12 10 8 6 4 2 0 -2 -4 1M 10 M 100 M 1G f - Frequency - Hz -3 dB 450 MHz RF = 249 , RL = 499 , VO = 1 VPP, VS = 3 V -3 dB 90 MHz -3 dB 85 MHz
3rd Harmonic Distortion - dBc 10 M 100 M
-60
-60
-70
-70
-80
-80
-90
-90
-100 1M f - Frequency - Hz
-100
1M
10 M f - Frequency - Hz
100 M
Figure 35. HARMONIC DISTORTION vs OUTPUT VOLTAGE
-40 Gain = 2 RL = 499 RF = 249 , f = 10 MHz, VS = 3 V 900 850 SR - Slew Rate - V/ s 800 750 Gain = 2, RF = 249 , RL = 499 , VS = 3 V
Figure 36. SLEW RATE vs OUTPUT VOLTAGE
1.75 Rise V O- Output Voltage - V 1.65
Figure 37.
SETTLING TIME
-50 Harmonic Distortion - dBc -60
Fall 700 650 600 550 500 450
1.55
-70
Gain = 2 RL = 499 RF = 249 VS = 3 V
1.45
-80 HD 2 -90 HD 3 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VO - Output Voltage - VPP 1
1.35
400 0 0.1 0.2 0.3 0.4 0.5 0.6 VO - Output Voltage - VPP
1.25 0 1 2 3 4 5 6 7 8 9 10 t - Time - ns
Figure 38.
Figure 39.
Figure 40.
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TYPICAL CHARACTERISTICS (3 V) (continued)
OUTPUT VOLTAGE vs LOAD RESISTANCE
2.25 VS = 3 V
I IB - Input Bias Current - A 9 8 7 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 IOS IIB+ VS = 3 V
INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE
640
INPUT OFFSET VOLTAGE vs CASE TEMPERATURE
2.5 VS = 3 V VOS - Input Offset Voltage - mV
620
2 VO - Output Voltage - V 1.75 1.5 1.25 1 0.75 0.5 10 100 RL - Load Resistance - m 1000
IIB-
600 580 560 540 520 500 480 460
OS - Input Offset Current - nA
2.25
2
1.75 1.5
1.25 1 -40 -20 0 20 40 60 80 TC - Case Temperature - C
I
TC - Case Temperature - C
Figure 41.
Figure 42.
Figure 43. OUTPUT IMPEDANCE vs FREQUENCY
10 k 1k 100 10 Gain = 2, RF = 249 , VS = 3 V
LARGE-SIGNAL TRANSIENT RESPONSE
Input 2 1.5 3 Output VO - Output Voltage - V 2.5 2 1.5 1 0.5 0 -10 0 10 Gain = 2, RF = 249 , RL = 499 , VS = 3 V 20 30 40 50 60 1 0.5 V I - Input Voltage - V 2.5
2.25 2 V O - Output Voltage - V PP 1.75 1.5 1.25 1 0.75 0.5
OVERDRIVE RECOVERY TIME
2.25 G = 2, RL = 499 , RF = 249 , VS = 3 V Input 2 1.75 1.5 1.25 Output 1 0.75 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t - Time - s 1
Z o - Output Impedance -
VI - Input Voltage - VPP
1 0.1 0.01 100 k 1M 10 M 100 M 1G f - Frequency - Hz
t - Time - ns
Figure 44.
Figure 45.
Figure 46.
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THS4304
www.ti.com
SLOS436A - MARCH 2004 - REVISED JULY 2004
APPLICATION INFORMATION
For many years, high-performance analog design has required the generation of split power supply voltages, like 15 V, 8 V, and more recently 5 V, in order to realize the full performance of the amplifiers available. Modern trends in high-performance analog are moving towards single-supply operation at 5 V, 3 V, and lower. This reduces power supply cost due to less voltages being generated and conserves energy in low power applications. It can also take a toll on available dynamic range, a valuable commodity in analog design, if the available voltage swing of the signal must also be reduced. Two key figures of merit for dynamic range are signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR). SNR is simply the signal level divided by the noise: Signal SNR + Noise and SFDR is the signal level divided by the highest spur: Signal SFDR + Spur In an operational amplifier, reduced supply voltage typically results in reduced signal levels due to lower voltage available to operate the transistors within the amplifier. When noise and distortion remain constant, the result is a commensurate reduction in SNR and SFDR. To regain dynamic range, the process and the architecture used to make the operational amplifier must have superior noise and distortion performance with lower power supply overhead required for proper transistor operation. The THS4304 BiCom3 operational amplifier is just such a device. It is able to provide 2-Vpp signal swing at its output on a single 5-V supply with noise and distortion performance similar to the best 10-V operational amplifiers on the market today
GENERAL APPLICATION
The THS4304 is a traditional voltage-feedback topology with wideband performance up to 3 GHz at unity gain. Care must be taken to ensure that parasitic elements do not erode the phase margin. Capacitance at the output and inverting input, and resistance and inductance in the feedback path, can cause problems. To reduce parasitic capacitance, the ground plane should be removed from under the part. To reduce inductance in the feedback, the circuit traces should be kept as short and direct as possible. For best performance in non-inverting unity gain (G=+1V/V), it is recommended to use a wide trace directly between the output and inverting input. For a gain of +2V/V, it is recommended to use a 249- feedback resistor. With good layout, this should keep the frequency response peaking to around 2 dB. This resistance is high enough to not load the output excessively, and the part is capable of driving 100- load with good performance. Higher-value resistors can be used, with more peaking. For example, 499 gives about 5 dB of peaking, and gives slightly better distortion performance with 100- load. Lower value feedback resistors can also be used to reduce peaking, but degrades the distortion performance with heavy loads. Power supply bypass capacitors are required for proper operation. The most critical are 0.1-F ceramic capacitors; these should be placed as close to the part as possible. Larger bulk capacitors can be shared with other components in the same area as the operational amplifier.
HARMONIC DISTORTION
For best second harmonic (HD2), it is important to use a single-point ground between the power supply bypass capacitors when using a split supply. It is also recommended to use a single ground or reference point for input termination and gain-setting resistors (R8 and R11 in the non-inverting circuit). It is recommended to follow the EVM layout closely in your application.
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THS4304
SLOS436A - MARCH 2004 - REVISED JULY 2004
www.ti.com
APPLICATION INFORMATION (continued)
SOT-23 versus MSOP With light loading of 500- and higher resistance, the THS4304 shows HD2 that is not dependant of package. With heavy output loading of 100 , the THS4304 in SOT-23 package shows about 6 dB better HD2 performance versus the MSOP package.
EVALUATION MODULES
The THS4304 has two evaluation modules (EVMs) available. One is for the MSOP (DGK) package and the other for the SOT-23 (DBV) package. These provide a convenient platform for evaluating the performance of the part and building various different circuits. The full schematics, board layout, and bill of materials (as supplied) for the boards are shown in the following illustrations.
-VS -VS VREF R3 R6 +VS C5 C1 GND TP1 C8 R8 C3 C2 C4 J3 FB1 GND GND J4 J6 +VS J5 FB2 +VS
R7 R9 +VS U1 J1 C7 R10 THS4304
-VS
C6* +VS
4 3
5 2
1
R2
C9
J2
R11
R1
R12* -VS *C6 - DGK EVM Only *R12 - DBV EVM Only
VREF
Figure 47. EVM Full Schematic
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THS4304
www.ti.com
SLOS436A - MARCH 2004 - REVISED JULY 2004
APPLICATION INFORMATION (continued)
EVM BILL OF MATERIALS
THS4304 EVM (1) Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (1) (2) (3) Description Bead, ferrite, 3-A, 80- Capacitor, 3.3-F, Ceramic Capacitor, 0.1-F, Ceramic Open Open Resistor, 0-, 1/10-W, 1% Resistor, 49.9-, 1/10-W, 1% Resistor, 249-, 1/10-W, 1% Jack, banana recepticle, 0.25-in. diameter hole Test point, black Connector, edge, SMA PCB jack Integrated Circuit, THS4304 Standoff, 4-40 HEX, 0.625-in. Length Screw, Phillips, 4-40, 0.250-in. Board, printed-circuit SMD Size 1206 1206 0603 0603 0603 0603 0603 0603 Reference Designator FB1, FB2 C1, C2 C4, C5 C3, C6 (2) R1, R3, R6, R9, R12 (3) C7. C8, C9, C10 R2, R11 R7, R8 J3, J4, J5, J6 TP1 J1, J2 U1 PCB Quantity 2 2 2 2 5 4 2 2 4 1 2 1 4 4 1 (KOA) RK73Z1JTTD (KOA) RK73H1JLTD49R9F (KOA) RK73H1JLTD2490F (HH SMITH) 101 (KEYSTONE) 5001 (JOHNSON) 142-0701-801 (TI) THS4304DGK, or (TI) THS4304DBV (KEYSTONE) 1808 SHR-0440-016-SN (TI) THS4304DGK ENG A, or (TI) THS4304DBV ENG A NEWARK) 89F1934 (GARRETT) RK73Z1JTTD (GARRETT) RK73H1JLTD49R9F (GARRETT) RK73H1JLTD2490F (NEWARK) 35F865 (DIGI-KEY) 5001K-ND (NEWARK) 90F2624 Manufacturer's Part Number (STEWARD) HI1206N800R-00 (AVX) 1206YG335ZAT2A (AVX) 0603YC104KAT2A Distributor's Part Number (DIGI-KEY) 240-1010-1-ND (GARRETT) 1206YG335ZAT2A (GARRETT) 0603YC104KAT2A
NOTE: All items are designated for both the DBV and DGK EVMs unless otherwise noted. C6 used on DGK EVM only. R12 used on DBV EVM only.
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THS4304
SLOS436A - MARCH 2004 - REVISED JULY 2004
www.ti.com
Figure 48. THS4304DGK EVM Layout Top and L2
Figure 49. THS4304DGK EVM Layout Bottom and L3
Figure 50. THS4304DBV EVM Layout Top and L2
Figure 51. THS4304DBV EVM Layout Bottom and L3
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THS4304
www.ti.com
SLOS436A - MARCH 2004 - REVISED JULY 2004
NON-INVERTING GAIN WITH SPLIT SUPPLY
The following schematic shows how to configure the operational amplifier for non-inverting gain with split power supply ( 2.5V). This is how the EVM is supplied from TI. This configuration is convenient for test purposes because most signal generators and analyzer are designed to use ground-referenced signals by default. Note the input and output provides 50- termination.
-VS -VS J3 FB1 GND J4 GND J6 +VS J5 FB2 +VS
C5 0.1 mF C8 0 R8 249 0 R7 249 0 +VS 4 C7 0 R10 0 R11 49.9 0 3 U1 5
C1 3.3 mF GND TP1
C2 3.3 mF
C4 0.1 mF
J1
1
R2 49.9 0
C9 0
J2
2 THS4304DBV -VS
Figure 52. Non-Inverting Gain with Split Power Supply
19
THS4304
SLOS436A - MARCH 2004 - REVISED JULY 2004
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INVERTING GAIN WITH SPLIT POWER SUPPLY
The following schematic shows how to configure the operational amplifier for inverting gain of 1 (-1 V/V) with split power supply (2.5 V). Note the input and output provides 50- termination for convenient interface to common test equipment.
-VS -VS J3 FB1 GND J4 GND J6 +VS J5 FB2 +VS
R7 249 0 J1 C7 0 R11 61.9 0 R9 221 0 +VS U1
C5 0.1 mF
C1 3.3 mF GND TP1
C2 3.3 mF
C4 0.1 mF
4 4 3
R1 124 0 C8 0
- +
5 2 2
1 1
THS4304DBV
R2 49.9 0
C9 0
J2
-VS
Figure 53. Inverting Gain with Split Power Supply
20
THS4304
www.ti.com
SLOS436A - MARCH 2004 - REVISED JULY 2004
NON-INVERTING SINGLE-SUPPLY OPERATION
The THS4304 EVM can easily be configured for single 5-V supply operation, as shown in the following schematic, with no change in performance. This circuit passes dc signals at the input, so care must be taken to reference (or bias) the input signal to mid-supply. If dc operation is not required, the amplifier can be ac coupled by inserting a capacitor in series with the input (C7) and output (C9).
VREF R3 10 km C8 R6 +VS 10 km R8 249 m R7 249 m GND TP1 +VS C2 3.3 F C4 0.1 F -VS J3 NC GND J4 GND J6 +VS J5 FB2 +VS
0.1 F
J1
C7 0
R10 0
4 4 3 3
R1 49.9 m
- +
U1 5 5 2 2
1 1
R2 49.9 m
C9 0
J2
THS4304DBV
C5 0
VREF
Figure 54. Non-Inverting 5-V Single-Supply Amplifier
DIFFERENTIAL ADC DRIVE AMPLIFIER
The circuit shown in Figure 54 is adapted as shown in Figure 55 to provide a high-performance differential amplifier drive circuit for use with high-performance ADCs, like the ADS5500 (14-bit 125-MSP ADC). For testing purposes, the circuit uses a transformer to convert the signal from a single-ended source to differential. If the input signal source in your application is differential and biased to mid-rail, no transformer is required. The circuit employs two amplifiers to provide a differential signal path to the ADS5500. A resistor divider (two 10-k resistors) is used to obtain a mid-supply reference voltage of 2.5 V (VREF) (the same as shown in the single-supply circuit of Figure 54). Applying this voltage to the one side of RG and to the positive input of the operational amplifier (via the center-tap of the transformer) sets the input and output common-mode voltage of the operational amplifiers to mid-rail to optimize their performance. The ADS5500 requires an input common-mode voltage of 1.5 V. Due to the mismatch in required common-mode voltage, the signal is ac coupled from the amplifier output, via the two 1-nF capacitors, to the input of the ADC. The CM voltage of the ADS5500 is used to bias the ADC input to the required voltage, via the 1-k resistors. Note: 100-A common-mode current is drawn by the ADS5500 input stage (at 125 MSPS). This causes a 100-mV shift in the input common-mode voltage, which does not impact the performance when driving the input to -1 dB of full scale. To offset this effect, a voltage divider from the power supply can be used to derive the input common-mode voltage reference. Because the operational amplifiers are configured as non-inverting, the inputs are high impedance. This is particularly useful when interfacing to a high-impedance source. In this situation, the amplifiers provide impedance matching and amplification of the signal. The SFDR performance of the circuit is shown in the following graph (see Figure 56) and provides for full performance from the ADS5500 to 40 MHz.
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THS4304
SLOS436A - MARCH 2004 - REVISED JULY 2004
www.ti.com
The differential topology employed in this circuit provides for significant suppression of the 2nd-order harmonic distortion of the amplifiers. This, along with the superior 3rd-order harmonic distortion performance of the amplifiers, results in the SFDR performance of the circuit (at frequencies up to 40 MHz) being set by higher-order harmonics generated by the sampling process of the ADS5500. The amplifier circuit (with resistor divider for bias voltage generation) requires a total of 185 mW of power from a single 5-V power supply.
+5 V
10 k 0 V REF (= 2 .5V ) RG V REF +5V + 3 .3 VA +3 .3 VD RF 10 k 0 0.1 mF
1 :1 V IN V REF From 50 0 source 49 .9 0
THS4304 100 0 +5V 1 nF CM 1k 0 THS4304 100 0 1 nF CM 0. 1 mF 1k 0 A IN+ ADS 5500 A IN- CM D A
V REF RG RF
Figure 55. Differential ADC Drive Amplifier Circuit
90 Combined THS4304 and ADS5500 SFDR 85 dB 80 G = 10 dB, -1 dBFS, RF = 249 , RG = 115 , SNR = 69.6, FS = 125 MSPS 10 20 30 40 50 75
f - Frequency - MHz
Figure 56. SFDR Performance versus Frequency - THS4304 Driving ADS5500
22
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